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hy5dv641622at 64m(4mx16) ddr sdram hy5dv641622at this document is a general product description and is subject to change without notice. hynix el ectronics does not assume any responsibility for use of circuits described. no patent licenses are implied. rev. 0.7/may. 02 1
rev. 0.7/may. 02 2 hy5dv641622at revision history 4. revision 0.7 (may. 02) 1) input leakage current chan ged from +/-5ua to +/-2ua 3. revision 0.6 (dec. 01) 1) separated ?function desc ription? and ?timin g diagram? parts - these are available in web site (www.hynix.com) 2. revision 0.5 (nov. 01) 1) changed tck maximum value a) 300/275mhz : changed from 4.5ns to 4.0ns b) 250/200mhz : changed from 8.0ns to 6.5ns 2) changed ?v ddq range? from +/- 0.2v to +/- 5% - changed from 2.3v/2.5 v/2.7v to 2.375v/2.5v/ 2.625v (min/typ/max) 1. revision 0.4 (sep. 01) 1) removed 183/166mhz parts from speed bin 2) changed cas latency from 3 to 4 at 300/275mhz 3) changed trcd from 5clk to 6clk at 300/275mhz 4) changed tck maximum value from 8ns to 4.5ns at 300/275mhz 5) changed v dd value a) 275mhz : changed from 3.15 v/3.30v/3.45v to 3.20v/3. 30v/3.45v (min/typ/max) b) 300mhz : changed from 3.15 v/3.30v/3.45v to 3.35v/3. 45v/3.55v (min/typ/max) 6) modified ?burst read followed by burst write? function - burst write command must be issued after (cl + bl/2 + 1) ticks of clock from burst read command, not (cl + bl/2) ticks of clock at 300/275mhz
description the hynix hy5dv641622 is a 67,108,864-bi t cmos double data rate(ddr) synchronous dram, ideally suited for the point-to-point applications wh ich requires high bandwidth. the hynix 4mx16 ddr sdrams offer fully synchronous operatio ns referenced to both rising and falling edges of the clock. while all addresses and control inpu ts are latched on the rising edges of th e ck (falling edges of the /ck), data, data strobes and write data masks inputs are sampled on both rising and falling edges of it. the data paths are inter- nally pipelined and 2-bit prefetched to achieve very high bandwidth. all input and output voltage levels are compatible with sstl_2. features ?3.3v for v dd and 2.5v for v ddq power supply ? all inputs and outputs are compatible with sstl_2 interface ? jedec standard 400mil 66pin tsop-ii with 0.65mm pin pitch ? fully differential clock in puts (ck, /ck) operation ? double data rate interface ? source synchronous - data transaction aligned to bidirectional data strobe (dqs) ? x16 device has 2 bytewide data strobes (ldqs, udqs) per each x8 i/o ? data outputs on dqs edges when read (edged dq) data inputs on dqs centers when write (centered dq) ? data(dq) and write masks(dm) latched on the both rising and falling edges of the data strobe ? all addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock ? write mask byte controls by ldm and udm ? programmable /cas latency 3 / 4 supported ? programmable burst length 2 / 4 / 8 with both sequential and interleave mode ? internal 4 bank operations with single pulsed /ras ? tras lock-out function supported ? auto refresh and self refresh supported ? 4096 refresh cycles / 64ms ? full, half and matched impedance(weak) strength driver option controlled by emrs ordering information part no. power supply clock frequency max data rate interface package hy5dv641622at-33 v dd =3.3v v ddq =2.5v 300mhz 600mbps/pin sstl_2 400mil 66pin tsop-ii hy5dv641622at-36 275mhz 550mbps/pin hy5dv641622at-4 250mhz 500mbps/pin HY5DV641622AT-5 200mhz 400mbps/pin hy5dv641622at rev. 0.7/may. 02 3
rev. 0.7/may. 02 4 hy5dv641622at pin configuration row and column address table items 4mx16 organization 1m x 16 x 4banks row address a0 ~ a11 column address a0 ~ a7 bank address ba0, ba1 auto precharge flag a10 refresh 4k 400mil x 875mil 66 pin tsop-ii 0.65mm pin pitch top view v dd dq0 vddq dq1 dq2 v ssq dq3 dq4 v ddq dq5 dq6 v ssq dq7 nc v ddq ldqs nc v dd nc ldm /we /cas /ras /cs nc ba0 ba1 a10/ap a0 a1 a2 a3 v dd v ss dq15 v ssq dq14 dq13 v ddq dq12 dq11 v ssq dq10 dq9 v ddq dq8 nc v ssq udqs nc v ref v ss udm /clk clk cke nc nc a11 a9 a8 a7 a6 a5 a4 v ss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34
rev. 0.7/may. 02 5 hy5dv641622at pin description pin type description ck, /ck input clock: ck and /ck are differen tial clock inputs. all address and control input signals are sampled on the crossing of the positive edge of ck and negative edge of /ck. output (read) data is referenced to the crossings of ck and /ck (both directions of crossing). cke input clock enable: cke high activa tes, and cke low deactivates internal clock signals, and device input buffers and output drivers. taking cke low provides precharge power down and self refresh operation (all ba nks idle), or active power down (row active in any bank). cke is synchronous fo r power down entry and exit, and for self refresh entry. cke is asynchronous for self refresh exit, and for output disable. cke must be maintained high throughout read and write accesses. input buffers, excluding ck, /ck and cke are disabled during powe r down. input buffers, excluding cke are disabled during self refresh. cke is an ss tl_2 input, but will detect an lvcmos low level after vdd is applied. /cs input chip select : enables or disables all inputs except ck, /ck, cke, dqs and dm. all com- mands are masked when cs is registered high. cs provides for external bank selection on systems with multiple banks. cs is considered part of the command code. ba0, ba1 input bank address inputs: ba0 and ba1 define to which bank an active, read, write or pre- charge command is being applied. a0 ~ a11 input address inputs: provide the row address for active commands, and the column address and auto precharge bit for read/write commands, to select one location out of the memory array in the respective bank. a10 is sampled during a precharge command to determine whether the precharge applies to one bank (a10 low) or all banks (a10 high). if only one bank is to be precharg ed, the bank is selected by ba0, ba1. the address inputs also provide the op code during a mode register set command. ba0 and ba1 define which mode register is loaded during the mode register set command (mrs or emrs). /ras, /cas, /we input command inputs: /ras, /cas and /we (along with /cs) define the command being entered. ldm, udm input input data mask: dm(ldm,udm) is an input mask signal for write data. input data is masked when dm is sampled high along with that input data during a write access. dm is sampled on both edges of dqs. althou gh dm pins are input only, the dm loading matches the dq and dqs loading. ldm corresponds to the data on dq0-q7; udm corre- sponds to the data on dq8-q15. ldqs, udqs i/o data strobe: output with read data, input with write data. edge aligned with read data, centered in write data. used to capture wr ite data. ldqs corresponds to the data on dq0-q7; udqs corresponds to the data on dq8-q15. dq0 ~ dq15 i/o data input / output pin : data bus v dd /v ss supply power supply for internal circuits and input buffers. v ddq /v ssq supply power supply for output buffers for noise immunity. v ref supply reference voltage for inputs for sstl interface. nc nc no connection.
rev. 0.7/may. 02 6 hy5dv641622at functional block diagram 4banks x 1mbit x 16 i/o double data rate synchronous dram command decoder clk /clk cke /cs /ras /cas /we ldm address buffer a0 ~ a11 bank control 1mx16/bank0 column decoder column address counter sense amp 2-bit prefetch unit 1mx16/bank1 1mx16/bank2 1mx16/bank3 mode register row decoder input buffer output buffer dll block mode register data strobe transmitter data strobe receiver ldqs, udqs clk ds write data register 2-bit prefetch unit ds dq[0:15] 32 16 16 32 clk_dll udm ba0, ba1
rev. 0.7/may. 02 7 hy5dv641622at simplified command truth table command cken-1 cken cs ras cas we addr a10/ ap ba note extended mode register set h x l l l l op code 1,2 mode register set h x l l l l op code 1,2 device deselect hx hxxx x1 no operation l h h h bank active h x l l h h ra v 1 read hxlhlhca l v 1 read with autoprecharge h1,3 write hxlhllca l v 1 write with autoprecharge h1,4 precharge all banks hxllhlx hx1,5 precharge selected bank lv1 read burst stop h x l h h l x 1 auto refresh h h lllh x 1 self refresh entryh l lllh x 1 exit l h hxxx 1 lhhh precharge power down mode entry h l hxxx x 1 lhhh 1 exit l h hxxx 1 lhhh 1 active power down mode entry h l hxxx x 1 lvvv 1 exit l h x 1 note : 1. ldm/udm states are don?t care. refer to below write mask truth table. 2. op code(operand code) consists of a0~a11 and ba0~ba1 us ed for mode register setting during extended mrs or mrs. before entering mode re gister set mode, all banks must be in a precharge state and mrs command can be issued after trp period from prechagre command. 3. if a read with autoprecharge command is detected by memory component in ck(n), then there will be no command presented to activated bank until ck(n+bl/2+trp). 4. if a write with autoprecharge command is detected by memory component in ck(n), then there will be no command presented to activated bank until ck(n+bl/2+1+tdpl+trp). last data-i n to prechage delay(tdpl) which is also called write recovery tim e (twr) is needed to guarantee that the last data has been completely written. 5. if a10/ap is high when precharge command being issued, ba0/ba1 are ignored and all banks are selected to be precharged. ( h=logic high level, l=logic low level, x=don?t care, v=va lid data input, op code=operand code, nop=no operation )
rev. 0.7/may. 02 8 hy5dv641622at write mask truth table function cken-1 cken /cs, /ras, /cas, /we ldm udm addr a10/ ap ba note data write h x x l l x 1,2 data-in mask h x x h h x 1,2 lower byte write / upper byte-in mask hx x lh x 1,2 upper byte write / lower byte-in mask hx x hl x 1,2 note : 1. write mask command masks burst write data with reference to ldqs/udqs(data strobes) and it is not related with read data. 2. ldm and udm control lower byte(dq0~7) and upper byte(dq8~15) respectively.
rev. 0.7/may. 02 9 hy5dv641622at operation command truth table - i current state /cs /ras /cas /we address command action idle hxxx x dsel nop or power down 3 lhhh x nop nop or power down 3 lhhl x bst illegal 4 l h l h ba, ca, ap read/readap illegal 4 l h l l ba, ca, ap write/writeap illegal 4 l l h h ba, ra act row activation llhl ba, ap pre/pall nop lllh x aref/sref auto refresh or self refresh 5 l l l l opcode mrs mode register set row active hxxx x dsel nop lhhh x nop nop lhhl x bst illegal 4 l h l h ba, ca, ap read/readap begin read : optional ap 6 l h l l ba, ca, ap write/writeap begin write : optional ap 6 llhhba, ra act illegal 4 llhl ba, ap pre/pall precharge 7 lllh x aref/sref illegal 11 llllopcode mrs illegal 11 read h x x x x dsel continue burst to end l h h h x nop continue burst to end lhhl x bst terminate burst l h l h ba, ca, ap read/readap term burst, new read:optional ap 8 l h l l ba, ca, ap write/writeap illegal llhhba, ra act illegal 4 l l h l ba, ap pre/pall term burst, precharge lllh x aref/sref illegal 11 llllopcode mrs illegal 11 write h x x x x dsel continue burst to end l h h h x nop continue burst to end lhhl x bst illegal 4 l h l h ba, ca, ap read/readap term burst, new read:optional ap 8 l h l l ba, ca, ap write/writeap term burst, new write:optional ap
rev. 0.7/may. 02 10 hy5dv641622at operation command truth table - ii current state /cs /ras /cas /we address command action write llhhba, ra act illegal 4 l l h l ba, ap pre/pall term burst, precharge lllh x aref/sref illegal 11 llllopcode mrs illegal 11 read with autopre- charge h x x x x dsel continue burst to end l h h h x nop continue burst to end lhhl x bst illegal l h l h ba, ca, ap read/readap illegal 10 l h l l ba, ca, ap write/writeap illegal 10 llhhba, ra act illegal 4,10 llhl ba, ap pre/pall illegal 4,10 lllh x aref/sref illegal 11 llllopcode mrs illegal 11 write autopre- charge h x x x x dsel continue burst to end l h h h x nop continue burst to end lhhl x bst illegal l h l h ba, ca, ap read/readap illegal 10 l h l l ba, ca, ap write/writeap illegal 10 llhhba, ra act illegal 4,10 llhl ba, ap pre/pall illegal 4,10 lllh x aref/sref illegal 11 llllopcode mrs illegal 11 pre- charge hxxx x dsel nop-enter idle after trp l h h h x nop nop-enter idle after trp lhhl x bst illegal 4 l h l h ba, ca, ap read/readap illegal 4,10 l h l l ba, ca, ap write/writeap illegal 4,10 llhhba, ra act illegal 4,10 l l h l ba, ap pre/pall nop-enter idle after trp lllh x aref/sref illegal 11 llllopcode mrs illegal 11
rev. 0.7/may. 02 11 hy5dv641622at operation command truth table - iii current state /cs /ras /cas /we address command action row activating h x x x x dsel nop - enter row act after trcd l h h h x nop nop - enter row act after trcd lhhl x bst illegal 4 l h l h ba, ca, ap read/readap illegal 4,10 l h l l ba, ca, ap write/writeap illegal 4,10 llhhba, ra act illegal 4,9,10 llhl ba, ap pre/pall illegal 4,10 lllh x aref/sref illegal 11 llllopcode mrs illegal 11 write recovering h x x x x dsel nop - enter row act after twr l h h h x nop nop - enter row act after twr lhhl x bst illegal 4 l h l h ba, ca, ap read/readap illegal l h l l ba, ca, ap write/writeap illegal llhhba, ra act illegal 4,10 llhl ba, ap pre/pall illegal 4,11 lllh x aref/sref illegal 11 llllopcode mrs illegal 11 write recovering with autopre- charge h x x x x dsel nop - enter precharge after tdpl l h h h x nop nop - enter precharge after tdpl lhhl x bst illegal 4 l h l h ba, ca, ap read/readap illegal 4,8,10 l h l l ba, ca, ap write/writeap illegal 4,10 llhhba, ra act illegal 4,10 llhl ba, ap pre/pall illegal 4,11 lllh x aref/sref illegal 11 llllopcode mrs illegal 11 refreshing h x x x x dsel nop - enter idle after trc l h h h x nop nop - enter idle after trc lhhl x bst illegal 11 l h l h ba, ca, ap read/readap illegal 11
rev. 0.7/may. 02 12 hy5dv641622at operation command truth table - iv note : 1. h - logic high level, l - logic low leve l, x - don?t care, v - valid data input, ba - bank address, ap - autoprecharge address, ca - column address, ra - row address, nop - no operation. 2. all entries assume that cke was active(high level) during the preceding clock cycle. 3. if both banks are idle and cke is inactive(low level), then in power down mode. 4. illegal to bank in specified state. function may be legal in the bank indicated by bank addr ess(ba) depending on the state o f that bank. 5. if both banks are idle and cke is inactive(low level), then self refresh mode. 6. illegal if trcd is not met. 7. illegal if tras is not met. 8. must satisfy bus contention, bus turn around, and/or write recovery requirements. 9. illegal if trrd is not met. 10. illegal for single bank, but legal for other banks in multi-bank devices. 11. illegal for all banks. current state /cs /ras /cas /we address command action write l h l l ba, ca, ap write/writeap illegal 11 llhhba, ra act illegal 11 llhl ba, ap pre/pall illegal 11 lllh x aref/sref illegal 11 llllopcode mrs illegal 11 mode register accessing h x x x x dsel nop - enter idle after tmrd l h h h x nop nop - enter idle after tmrd lhhl x bst illegal 11 l h l h ba, ca, ap read/readap illegal 11 l h l l ba, ca, ap write/writeap illegal 11 llhhba, ra act illegal 11 llhl ba, ap pre/pall illegal 11 lllh x aref/sref illegal 11 llllopcode mrs illegal 11
rev. 0.7/may. 02 13 hy5dv641622at cke function truth table note : when cke=l, all dq and dqs must be in hi-z state. 1. cke and /cs must be kept high for a minimum of 200 stable input clocks before issuing any command. 2. all command can be stored after 2 clocks from low to high transition of cke. 3. illegal if ck is suspended or stopped during the power down mode. 4. self refresh can be entered on ly from the all banks idle state. 5. disabling ck may cause malfunction of any bank which is in active state. current state cken- 1 cken /cs /ras /cas /we /add action self refresh 1 h xxxxxx invalid l h h x x x x exit self refresh, enter idle after tsrex l h l h h h x exit self refresh, enter idle after tsrex lhlhhlx illegal lhlhlxx illegal lhllxxx illegal l lxxxxx nop, continue self refresh power down 2 h xxxxxx invalid l h h x x x x exit power down, enter idle l h l h h h x exit power down, enter idle lhlhhlx illegal lhlhlxx illegal lhllxxx illegal l l x x x x x nop, continue power down mode all banks idle 4 h h x x x x x see operation command truth table hllllhx enter self refresh h l h x x x x exit power down h l l h h h x exit power down hllhhlx illegal hllhlxx illegal hlllhxx illegal hlllllx illegal l lxxxxx nop any state other than above h h x x x x x see operation command truth table h lxxxxx illegal 5 l hxxxxx invalid l lxxxxx invalid
rev. 0.7/may. 02 14 hy5dv641622at simplified state diagram mrs sref srex pden pdex act aref pdex pden bst read write write writeap writeap read readap readap pre(pall) pre(pall) pre(pall) command input automatic sequence idle auto refresh pre- charge power-up power applied mode register set power down write with autopre- charge power down write read with autopre- charge bank active read self refresh
rev. 0.7/may. 02 15 hy5dv641622at power-up sequence and device initialization ddr sdrams must be powered up and initialized in a pred efined manner. operational procedures other than those specified may result in undefined operation. power must first be applied to v dd , then to v ddq , and finally to v ref (and to the system v tt ). v tt must be applied after v ddq to avoid device latch-up, whic h may cause permanent damage to the device. v ref can be applied anytime after v ddq , but is expected to be no minally coincident with v tt . except for cke, inputs are not recognized as valid until after v ref is applied. cke is an sstl_2 in put, but will detect an lvcmos low level after v dd is applied. maintaining an lvcm os low level on cke during powe r-up is required to guarantee that the dq and dqs outputs will be in the high-z state, where they will remain until driven in normal operation (by a read access). after all power supply and reference volt ages are stable, and the clock is stable, the ddr sdram requires a 200us delay prior to applying an executable command. once the 200us delay has been satisfied, a deselect or nop command should be applied, and cke should be brought high. following the nop command, a precharg e all command should be applied. next a extended mode register set command should be issued for the ex tended mode register, to en able the dll, then a mode register set command should be issued for the mode register, to reset th e dll, and to program the operating parameters. 200 clock cycles are required between the dll reset and any command. during the 200 cycles of ck, for dll locking, executable commands are disallowed (a de select or nop command must be applied). after the 200 clock cycles, a precharge all command should be applied, placing the device in the all banks idle state. once in the idle state, two auto refresh cycles must be performed. additionally, a mode register set command for the mode register with the reset dll bit deactivated (i .e. to program operating parameters without resetting the dll) must be performed. following these cycles , the ddr sdram is ready for normal operation. 1. apply power - v dd , v ddq , v tt , v ref in the following power up sequencing and attempt to maintain cke at lvc- mos low state. (all the other input pins may be undefined.) ?v dd and v ddq are driven from a single power converter output. ?v tt is limited to 1.44v (reflecting vddq(max)/ 2 + 50mv vref variation + 40mv vtt variation. ?v ref tracks v ddq /2. ? a minimum resistance of 42 ohms (22 ohm series resistor + 22 ohm parallel resistor - 5% tolerance) limits the input current from the v tt supply into any pin. ? if the above criteria cannot be met by the system desi gn, then the following sequen cing and voltage relation- ship must be adhered to during power up. 2. start clock and maintain stable clock for a minimum of 200usec. 3. after stable power and clock, apply nop condition and take cke high. 4. issue extended mode register set (emrs) to enable dll. 5. issue mode register set (mrs) to reset dll and set devi ce to idle state with bit a8=high. (an additional 200 cycles of clock are required for locking dll) 6. issue precharge commands for all banks of the device. votage description sequencing voltage relationship to avoid latch-up v ddq after or with v dd < v dd + 0.3v v tt after or with v ddq < v ddq + 0.3v v ref after or with v ddq < v ddq + 0.3v
rev. 0.7/may. 02 16 hy5dv641622at 7. issue 2 or more auto refresh commands. 8. issue a mode register set command to initia lize the mode register with bit a8 = low. power-up sequence /clk clk vdd ldqs, udqs dq?s mrs aref pre nop mrs emrs pre nop code code code code code code code code code vddq vref cke cmd ba0,ba1 a10 addr ldm,udm ? ???? ? ? ?? ? ? ? ?? ? ? ?? ? ? ?? ? ? tvtd t=200usec tmrd 200 cycles of ck* trp trfc power up vdd and ck stable precharge all emrs set mrs set reset dll (with a8=h) precharge all 2 or more auto refresh mrs set (with a8=l) *200 cycles of ck are required (for dll locking) before any executable command can be applied. vtt trp tis tih
rev. 0.7/may. 02 17 hy5dv641622at mode register set (mrs) the mode register is used to store the various operating mo des such as /cas latency, addressing mode, burst length, burst type, test mode, dll reset. the mode register is pr ogram via mrs command. this command is issued by the low signals of /ras, /cas, /cs, /we and ba0. this command can be issued only when all bank s are in idle state and cke must be high at least one cycle before the mode regist er set command can be issued. two cycles are required to write the data in mode register. during the the mrs cycle, any command cannot be issued. once mode register field is determined, the information will be held until resetted by another mrs command. ba1 ba0 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0 0 rfu dr tm cas latency bt burst length a2 a1 a0 burst length sequential interleave 0 0 0 reserved reserved 001 2 2 010 4 4 011 8 8 1 0 0 reserved reserved 1 0 1 reserved reserved 1 1 0 reserved reserved 1 1 1 reserved reserved a3 burst type 0 sequential 1 interleave a6 a5 a4 cas latency 000 reserved 001 reserved 010 reserved 011 3 100 4 101 reserved 110 reserved 111 reserved a7 te s t mo de 0normal 1 test a8 dll reset 0no 1yes ba0 mrs type 0mrs 1emrs
rev. 0.7/may. 02 18 hy5dv641622at burst definition burst length & type read and write accesses to the ddr sdram are burst orient ed, with the burst length be ing programmable. the burst length determines the maximum number of column locations that can be accessed for a given read or write com- mand. burst lengths of 2, 4 or 8 locations are available for both the sequential and the interleaved burst types. reserved states should not be used, as unknown operatio n or incompatibility with future versions may result. when a read or write command is issued, a block of column s equal to the burst length is effectively selected. all accesses for that burst take place within this block, mean ing that the burst wraps within the block if a boundary is reached. the block is uniquely selected by a1-ai when the burst length is set to two, by a2-ai when the burst length is set to four and by a3-ai when the burst le ngth is set to eight (where ai is the most significant column address bit for a given configuration). the remaining (least significant) address bit(s) is (are) used to select the starting location within the block. the programmed burst length applies to both read and write bursts. accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit a3. the ordering of acce sses within a burst is determined by the burst length, the burst type and the starting column addres s, as shown in burst definitionon table burst length starting address (a2,a1,a0) sequential interleave 2 xx0 0, 1 0, 1 xx1 1, 0 1, 0 4 x00 0, 1, 2, 3 0, 1, 2, 3 x01 1, 2, 3, 0 1, 0, 3, 2 x10 2, 3, 0, 1 2, 3, 0, 1 x11 3, 0, 1, 2 3, 2, 1, 0 8 000 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 001 1, 2, 3, 4, 5, 6, 7, 0 1, 0, 3, 2, 5, 4, 7, 6 010 2, 3, 4, 5, 6, 7, 0, 1 2, 3, 0, 1, 6, 7, 4, 5 011 3, 4, 5, 6, 7, 0, 1, 2 3, 2, 1, 0, 7, 6, 5, 4 100 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 101 5, 6, 7, 0, 1, 2, 3, 4 5, 4, 7, 6, 1, 0, 3, 2 110 6, 7, 0, 1, 2, 3, 4, 5 6, 7, 4, 5, 2, 3, 0, 1 111 0, 1, 2, 3, 4, 5, 6, 7 7, 6, 5, 4, 3, 2, 1, 0
rev. 0.7/may. 02 19 hy5dv641622at cas latency the read latency or cas latency is the delay in clock cy cles between the registration of a read command and the availability of the first burst of output data . the latency can be programmed 3 or 4 clocks. if a read command is registered at clock edge n, and the la tency is m clocks, the data is available nominally coincident with clock edge n + m. reserved states should not be used as unknown operation or incompatibility with future versions may result. dll reset the dll must be enabled for normal operation. dll enable is required during power up in itialization, and upon return- ing to normal operation after having di sabled the dll for the purpose of debug or evaluation. the dll is automatically disabled when entering self refresh operation and is automatically re-enabled upon exit of self refresh operation. any time the dll is enabled, 200 clock cycles must occur to al low time for the internal cloc k to lock to the externally applied clock before an any command can be issued. output driver impedance control the hy5dv641622a supports full, half strength driver and ma tched impedance driver, intended for lighter load and/or point-to-point environments. the full dr ive strength for all output is specified to be sstl_2, class ii. half strength driver is to define about 50% of full drive strength and matched impedance driver, about 30% of full drive strength.
rev. 0.7/may. 02 20 hy5dv641622at extended mode register set (emrs) the extended mode register controls fu nctions beyond those contro lled by the mode register; these additional func- tions include dll enable/disable, output driver strength sele ction(optional). these function s are controlled via the bits shown below. the extended mode register is programmed via the mode register set command ( ba0=1 and ba1=0) and will retain the stored information until it is programmed again or the device loses power. the extended mode register must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating any subseque nt operation. violating either of these requirements will result in unspecified operation. ba1 ba0 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0 1 rfu* ds rfu* ds dll a0 dll enable 0enable 1diable ba0 mrs type 0mrs 1emrs * all bits in rfu address fields must be programmed to zero, all other states are reserved for future usage. a6 a1 output driver impedance control 00 full 0 1 half 10 rfu* 1 1 matched impedance (weak)
rev. 0.7/may. 02 21 hy5dv641622at absolute maximum ratings note : operation at above absolute maximum rating can adversely affect device reliability dc operating conditions (ta=0 to 70 o c, voltage referenced to v ss = 0v) note : 1. v dd specification for 250/200mhz 2. v dd specification for 275mhz 3. v dd specification for 300mhz 4. v ddq must not exceed the level of v dd . 5. v il (min) is acceptable -1.5v ac pulse width with 5ns of duration. 6. v ref is expected to be equal to 0.5*v ddq of the transmitting device, and to track variations in the dc level of the same. peak to peak noise on v ref may not exceed 2% of the dc value. parameter symbol rating unit ambient temperature t a 0 ~ 70 o c storage temperature t stg -55 ~ 125 o c voltage on any pin relative to v ss v in , v out -0.5 ~ 3.6 v voltage on v dd relative to v ss v dd -0.5 ~ 3.6 v voltage on v ddq relative to v ss v ddq -0.5 ~ 3.6 v output short circuit current i os 50 ma power dissipation p d 1w soldering temperature ? time t solder 260 ? 10 o c ? sec parameter symbol min typ. max unit note power supply voltage v dd 3.15 3.3 3.45 v 1 3.2 3.3 3.45 v 2 3.35 3.45 3.55 v 3 power supply voltage v ddq 2.375 2.5 2.625 v 4 input high voltage v ih v ref + 0.15 - v ddq + 0.3 v input low voltage v il -0.3 - v ref - 0.15 v 5 termination voltage v tt v ref - 0.04 v ref v ref + 0.04 v reference voltage v ref 0.49*v ddq 0.5*v ddq 0.51*v ddq v6
rev. 0.7/may. 02 22 hy5dv641622at dc characteristics i (ta=0 to 70 o c, voltage referenced to v ss = 0v) note : 1. v in = 0 to 3.6v, all other pins are not tested under v in = 0v. 2. d out is disabled, v out = 0 to 2.7v dc characteristics ii (ta=0 to 70 o c, voltage referenced to v ss = 0v) note : 1. i dd1, idd4 and i dd5 depend on output loading and cycle rates. spec ified values are measured with the output open. 2. min. of t rfc (auto refresh row cycle time) is shown at ac characteristics. parameter symbol min. max unit note input leakage current i li -2 2 ua 1 output leakage current i lo -5 5 ua 2 output high voltage v oh v tt + 0.76 - v i oh = -15.2ma output low voltage v ol -v tt - 0.76 v i ol = +15.2ma parameter symbol test condition speed unit note 33 36 4 5 operating current i dd1 b u r s t l e n g th = 2, o n e b a n k a c ti ve t rc t rc (min), i ol =0ma 150 130 120 100 ma 1 precharge standby current in power down mode i dd2p cke v il (max), t ck = min 20 ma precharge standby current in non power down mode i dd2n cke v ih (min), cs v ih (min), t ck = min input signals are changed one time during 2clks 100 90 80 70 ma active standby current in power down mode i dd3p cke v il (max), t ck = min 20 ma active standby current in non power down mode i dd3n cke v ih (min), cs v ih (min), t ck = min input signals are changed one time during 2clks 100 90 80 70 ma burst mode operating current i dd4 t ck t ck (min), i ol = 0ma all banks active 250 230 210 190 ma 1 auto refresh current i dd5 t rc t rfc (min), all banks active 200 ma 1,2 self refresh current i dd6 cke 0.2v 2 ma
rev. 0.7/may. 02 23 hy5dv641622at ac operating conditions (ta=0 to 70 o c, voltage referenced to v ss = 0v) note : 1. vid is the magnitude of the difference betw een the input level on ck and the input on ck. 2. the value of vix is expected to equal 0.5*v ddq of the transmitting device and must track variations in the dc level of the same. ac operating test conditions (ta=0 to 70 o c, voltage referenced to vss = 0v) parameter symbol min max unit note input high (logic 1) voltag e, dq, dqs and dm signals v ih(ac) v ref + 0.35 v input low (logic 0) voltag e, dq, dqs and dm signals v il(ac) v ref - 0.35 v input differential voltage, ck and /ck inputs v id(ac) 0.7 v ddq + 0.6 v 1 input crossing point voltage, ck and /ck inputs v ix(ac) 0.5*v ddq -0.2 0.5*v ddq +0.2 v 2 parameter value unit reference voltage v ddq x 0.5 v termination voltage v ddq x 0.5 v ac input high level voltage (v ih , min) v ref + 0.35 v ac input low level voltage (v il , max) v ref - 0.35 v input timing measurement reference level voltage v ref v output timing measurement reference level voltage v tt v input signal maximum peak swing 1.5 v input minimum signal slew rate 1 v/ns termination resistor (r t )50 ? series resistor (r s )25 ? output load capacitance for access time measurement (c l )30 pf
rev. 0.7/may. 02 24 hy5dv641622at ac characteristics - i (ac operating conditions unless otherwise noted) parameter symbol 33 36 4 5 unit note min max min max min max min max row cycle time t rc 52.8-54-56-60-ns auto refresh row cycle time t rfc 72 - 72 - 72 - 75 - ns row active time t ras 36.3 120k 36 120k 36 120k 40 120k ns row address to column address delay t rcd 6-6-5-4-ck row active to row active delay t rrd 2-2-2-2-ck column address to column address delay t ccd 1-1-1-1-ck row precharge time t rp 5-5-5-4-ck last data-in to precharge delay time (write recovery time : twr) t dpl 3-3-2-2-ck last data-in to read command t drl 2-2-2-1-ck auto precharge write recovery + precharge time t dal 8-8-7-6-ck system clock cycle time cl = 4.0 t ck 3.3 4.0 3.6 4.0 - - - - ns cl = 3.0 t ck ----46.556.5ns clock high level width t ch 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 ck clock low level width t cl 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 ck data-out edge to clock edge skew t ac -1.00.5-1.00.5-1.00.5-1.00.5ns dqs-out edge to clock edge skew t dqsck -1.00.5-1.00.5-1.00.5-1.00.5ns dqs-out edge to data-out edge skew t dqsq - 0.4 - 0.4 - 0.4 - 0.4 ns data-out hold time from dqs t qh t hpmin -t qhs - t hpmin -t qhs - t hpmin -t qhs - t hpmin -t qhs -ns1, 6 clock half period t hp t ch/l min - t ch/l min - t ch/l min - t ch/l min -ns1, 5 data hold skew factor t qhs -0.4-0.4-0.4-0.75ns6 input setup time t is 0.9 - 0.9 - 0.9 - 0.9 - ns 2 input hold time t ih 0.9 - 0.9 - 0.9 - 0.9 - ns 2 write dqs high level width t dqsh 0.40.60.40.60.40.60.40.6ck write dqs low level width t dqsl 0.40.60.40.60.40.60.40.6ck clock to first rising edge of dqs-in t dqss 0.8 1.25 0.8 1.25 0.8 1.25 0.75 1.25 ck
rev. 0.7/may. 02 25 hy5dv641622at n ote : 1. this calculation accounts for tdqsq(max), the pulse width distortion of on-chip circuit and jitter. 2. data sampled at the rising edges of the cloc k : a0~a11, ba0~ba1, cke, /cs, /ras, /cas, /we. 3. data latched at both rising and falling ed ges of data strobes(ldqs/udqs) : dq, ldm/udm. 4. minimum of 200 cycles of stable input clocks after self refresh exit command, where cke is held high, is required to complet e self refresh exit and lock th e internal dll circuit of ddr sdram. 5. min (tcl, tch) refers to the smaller of the actual clock low ti me and the actual cloc k high time as provided to the device ( i.e. this value can be greater than the mini mum specification limi ts for tcl and tch). 6. thp = minimum half clock period for any given cycle and is de fined by clock high or clock low (tch, tcl). tqhs consists of tdqsqmax, the pulse width distortion of on-chip clock circuits, data pin to pin skew and output pattern effects, and p-chan nel to n-channel variation of the output drivers. 7. dqs, dm and dq input slew rate is specified to prevent double clocking of data and preserve setup and hold times. signal transitions through the dc region must be monotonic. data-in setup time to dqs-in (dq & dm) t ds 0.4 - 0.4 - 0.4 - 0.5 - ns 3 data-in hold time to dqs-in (dq & dm) t dh 0.4 - 0.4 - 0.4 - 0.5 - ns 3 read dqs preamble time t rpre 0.91.10.91.10.91.10.91.1ck read dqs postamble time t rpst 0.40.60.40.60.40.60.40.6ck write dqs preamble setup time t wpres 0-0-0-0-ns write dqs preamble hold time t wpreh 1.5 - 1.5 - 1.5 - 1.5 - ns write dqs postamble time t wpst 0.40.60.40.60.40.60.40.6ck mode register set delay t mrd 3-3-3-2-ck exit self refresh to any execute command t xsc 200 - 200 - 200 - 200 - ck 4 average periodic refresh interval t refi - 15.6 - 15.6 - 15.6 - 15.6 us parameter symbol 33 36 4 5 unit note min max min max min max min max
rev. 0.7/may. 02 26 hy5dv641622at capacitance (t a =25 o c, f=1mhz ) note : 1. v dd = min. to max., v ddq = 2.3v to 2.7v, v o dc = v ddq /2, v o peak-to-peak = 0.2v 2. pins not under test are tied to gnd. 3. these values are guaranteed by desi gn and are tested on a sample basis only. output load circuit parameter pin symbol min max unit input clock capacitance ck, ck c ck 2.0 3.0 pf input capacitance all other input-only pins c in 2.0 3.0 pf input / output capacitanc dq, dqs, dm c io 4.0 5.0 pf v ref v tt v tt r t =50 ? r t =50 ? r s =25 ? zo=50 ? c l =30pf output
rev. 0.7/may. 02 27 hy5dv641622at 10.26 (0.404) 10.05 (0.396) 11.94 (0.470) 11.79 (0.462) 22.33 (0.879) 22.12 (0.871) 1.194 (0.0470) 0.991 (0.0390) 0.65 (0.0256) bsc 0.35 (0.0138) 0.25 (0.0098) 0.15 (0.0059) 0.05 (0.0020) base plane seating plane 0.597 (0.0235) 0.406 (0.0160) 0.210 (0.0083) 0.120 (0.0047) 0 ~ 5 deg. unit : mm(inch) package information 400mil 66pin thin small outline package note : package do not mold protrusion. allowable protrusion of both sides is 0.4mm.

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